This invention relates to device lithography and, more particularly, to the fabrication of integrated circuits utilizing thick high-resolution patterns.
Providing adequate step coverage in lithographic processes designed to make high-resolution integrated circuits is a vexing problem. High resolution implies utilizing very thin layers of resist for pattern delineation on the surface of a device wafer being processed. But to achieve satisfactory coverage over steps on a nonplanar surface of such a device, the resist layer must as a practical matter be made thicker than is dictated by resolution considerations alone. Thus, the resist layer thickness utilized in actual fabrication processes is usually thicker than would be specified if resolution were the only factor to be considered but thinner than if absolutely reliable step coverage were the sole consideration.
Moreover, a relatively thin resist layer applied to a nonplanar surface typically exhibits a variable thickness. In turn, patterning such a layer usually results in device feature geometries whose sizes vary as a function of resist thickness. Such feature or linewidth changes may lead to geometrical variations that are sufficiently serious to cause defects or at least less-than-optimal performance in the device being fabricated. Thus, good feature or linewidth control is obviously an important desideratum of a reliable high-yield integrated circuit fabrication process.
As the trend toward large-scale and very-large-scale integrated circuits has continued, considerable effort has been directed at trying to devise improved fine-line patterning techniques characterized by high resolution, good step coverage and good linewidth control. It was recognized that such techniques, if available, would improve the results obtainable with available lithographic systems and thereby lower the cost and improve the performance of integrated circuits made thereby.